A Tunnel FET for R Asra, M Shrivastava, KVRM Murali, RK Pandey, H Gossner, VR Rao
IEEE Transactions on Electron Devices 58 (7), 1855-1863, 2011
193 2011 Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures M Shrivastava, M Agrawal, S Mahajan, H Gossner, T Schulz, DK Sharma, ...
IEEE Transactions on Electron Devices 59 (5), 1353-1363, 2012
116 2012 A review on the ESD robustness of drain-extended MOS devices M Shrivastava, H Gossner
IEEE Transactions on Device and Materials Reliability 12 (4), 615-625, 2012
91 2012 Part I: Physical insight into carbon-doping-induced delayed avalanche action in GaN buffer in AlGaN/GaN HEMTs V Joshi, SP Tiwari, M Shrivastava
IEEE Transactions on Electron Devices 66 (1), 561-569, 2018
68 2018 A comprehensive computational modeling approach for AlGaN/GaN HEMTs V Joshi, A Soni, SP Tiwari, M Shrivastava
IEEE Transactions on Nanotechnology 15 (6), 947-955, 2016
61 2016 Part I: Mixed-signal performance of various high-voltage drain-extended MOS devices M Shrivastava, MS Baghini, H Gossner, VR Rao
IEEE transactions on electron devices 57 (2), 448-457, 2009
60 2009 A roadmap for disruptive applications and heterogeneous integration using two-dimensional materials: State-of-the-art and technological challenges M Shrivastava, V Ramgopal Rao
Nano letters 21 (15), 6359-6381, 2021
57 2021 A novel bottom spacer FinFET structure for improved short-channel, power-delay, and thermal performance M Shrivastava, MS Baghini, DK Sharma, VR Rao
IEEE Transactions on Electron Devices 57 (6), 1287-1294, 2010
57 2010 Novel Drain-Connected Field Plate GaN HEMT Designs for Improved V BD –R ON Tradeoff and RF PA Performance A Soni, M Shrivastava
IEEE Transactions on Electron Devices 67 (4), 1718-1725, 2020
55 2020 Fin enabled area scaled tunnel FET K Hemanjaneyulu, M Shrivastava
IEEE Transactions on Electron Devices 62 (10), 3184-3191, 2015
54 2015 High voltage semiconductor devices M Shrivastava, MS Baghini, CC Russ, H Gossner, R Rao
US Patent 8,664,720, 2014
50 2014 A novel and robust approach for common mode feedback using IDDG FinFET M Shrivastava, MS Baghini, AB Sachid, DK Sharma, VR Rao
IEEE Transactions on Electron Devices 55 (11), 3274-3282, 2008
48 2008 Toward system on chip (SoC) development using FinFET technology: Challenges, solutions, process co-development & optimization guidelines M Shrivastava, R Mehta, S Gupta, N Agrawal, MS Baghini, DK Sharma, ...
IEEE Transactions on Electron Devices 58 (6), 1597-1607, 2011
47 2011 Positive Threshold Voltage Shift in AlGaN/GaN HEMTs and E-Mode Operation By SD Gupta, A Soni, V Joshi, J Kumar, R Sengupta, H Khand, B Shankar, ...
IEEE Transactions on Electron Devices 66 (6), 2544-2550, 2019
40 2019 Part II: Proposals to independently engineer donor and acceptor trap concentrations in GaN buffer for ultrahigh breakdown AlGaN/GaN HEMTs V Joshi, SP Tiwari, M Shrivastava
IEEE Transactions on Electron Devices 66 (1), 570-577, 2018
39 2018 Record low metal—(CVD) graphene contact resistance using atomic orbital overlap engineering A Meersha, HB Variar, K Bhardwaj, A Mishra, S Raghavan, N Bhat, ...
2016 IEEE International Electron Devices Meeting (IEDM), 5.3. 1-5.3. 4, 2016
37 2016 Sub 0.5 V operation of performance driven mobile systems based on area scaled tunnel FET devices A Rajoriya, M Shrivastava, H Gossner, T Schulz, VR Rao
IEEE transactions on electron devices 60 (8), 2626-2633, 2013
37 2013 A novel drain-extended FinFET device for high-voltage high-speed applications M Shrivastava, H Gossner, VR Rao
IEEE Electron Device Letters 33 (10), 1432-1434, 2012
35 2012 Part II: On the three-dimensional filamentation and failure modeling of STI type DeNMOS device under various ESD conditions M Shrivastava, H Gossner, MS Baghini, VR Rao
IEEE transactions on electron devices 57 (9), 2243-2250, 2010
35 2010 Part I: On the unification of physics of quasi-saturation in LDMOS devices BS Kumar, M Shrivastava
IEEE Transactions on Electron Devices 65 (1), 191-198, 2017
32 2017 