Rangharajan Venkatesan

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Brucek KhailanySenior Director of VLSI Research, NVIDIADirección de correo verificada de cva.stanford.edu
William DallyChief Scientist, NVIDIA; Adjunct Professor of CS and EE, Stanford University;Dirección de correo verificada de stanford.edu
Anand RaghunathanSilicon Valley Chair Professor of Electrical and Computer Engineering, Purdue UniversityDirección de correo verificada de purdue.edu
Kaushik RoyProfessor of Electrical and Computer Engineering, Purdue UniversityDirección de correo verificada de purdue.edu
Steve KecklerVice President of Architecture Research, NVIDIADirección de correo verificada de cs.utexas.edu
Joel EmerProfessor of the Practice, MIT - Sr. Distinguished Research Scientist, NvidiaDirección de correo verificada de csail.mit.edu
Brian ZimmerSenior Research Scientist, NVIDIADirección de correo verificada de nvidia.com
Yakun Sophia ShaoAssociate Professor, UC BerkeleyDirección de correo verificada de berkeley.edu
Jason ClemonsNVIDIA - Senior Research ScientistDirección de correo verificada de nvidia.com
Steve DaiNVIDIA ResearchDirección de correo verificada de nvidia.com
Nathaniel PinckneyNVIDIADirección de correo verificada de umich.edu
Priyanka RainaAssistant Professor, Stanford UniversityDirección de correo verificada de stanford.edu
Alicia KlinefelterResearch Scientist at NVidiaDirección de correo verificada de nvidia.com
Yanqing ZhangNVIDIADirección de correo verificada de virginia.edu
Nan JiangNVIDIADirección de correo verificada de stanford.edu
Angshuman ParasharSr. Research Scientist, NVIDIADirección de correo verificada de nvidia.com
Mrigank SharadAssistant Professor Grade-I, Rajendra Mishra School of Engg Entrepreneurship, IIT KharagpurDirección de correo verificada de rediffmail.in
Xuanyao FongNational University of SingaporeDirección de correo verificada de nus.edu.sg
Anurag MukkaraPhD Student, MIT CSAILDirección de correo verificada de csail.mit.edu
Vivek Joy KozhikkottuResearch Scientist, Intel CorpDirección de correo verificada de intel.com

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Rangharajan Venkatesan

Senior Research Scientist

Dirección de correo verificada de nvidia.com - Página principal

Deep Learning Hardware-Software Co-design High-level Synthesis Spintronic Memories


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SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017	1539	2017
Timeloop: A systematic approach to dnn accelerator evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... 2019 IEEE international symposium on performance analysis of systems and …, 2019	507	2019
Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd annual IEEE/ACM international symposium on …, 2019	479	2019
MACACO: Modeling and analysis of circuits for approximate computing R Venkatesan, A Agarwal, K Roy, A Raghunathan 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 667-673, 2011	344	2011
Spin-transfer torque memories: Devices, circuits, and systems X Fong, Y Kim, R Venkatesan, SH Choday, A Raghunathan, K Roy Proceedings of the IEEE 104 (7), 1449-1488, 2016	218	2016
TapeCache: A high density, energy efficient cache based on domain wall memory R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ... Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012	174	2012
Magnet: A modular accelerator generator for neural networks R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019	139	2019
A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020	117	2020
Dwm-tapestri-an energy efficient all-spin cache using domain wall shift based writes R Venkatesan, M Sharad, K Roy, A Raghunathan 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013	115	2013
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing SG Ramasubramanian, R Venkatesan, M Sharad, K Roy, A Raghunathan Proceedings of the 2014 international symposium on Low power electronics and …, 2014	106	2014
Softermax: Hardware/software co-design of an efficient softmax for transformers JR Stevens, R Venkatesan, S Dai, B Khailany, A Raghunathan 2021 58th ACM/IEEE Design Automation Conference (DAC), 469-474, 2021	100	2021
Stag: Spintronic-tape architecture for gpgpu cache hierarchies R Venkatesan, SG Ramasubramanian, S Venkataramani, K Roy, ... ACM SIGARCH Computer Architecture News 42 (3), 253-264, 2014	85	2014
Accelerating chip design with machine learning B Khailany Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 33-33, 2020	83	2020
Analog/mixed-signal hardware error modeling for deep learning inference AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019	81	2019
A modular digital VLSI flow for high-productivity SoC design B Khailany, E Khmer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018	78	2018
Buffets: An efficient and composable storage idiom for explicit decoupled data orchestration M Pellauer, YS Shao, J Clemons, N Crago, K Hegde, R Venkatesan, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019	77	2019
Vs-quant: Per-vector scaled quantization for accurate low-precision neural network inference S Dai, R Venkatesan, M Ren, B Zimmer, W Dally, B Khailany Proceedings of Machine Learning and Systems 3, 873-884, 2021	76	2021
A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... 2019 Symposium on VLSI Circuits, C300-C301, 2019	57	2019
STAxCache: An approximate, energy efficient STT-MRAM cache A Ranjan, S Venkataramani, Z Pajouhi, R Venkatesan, K Roy, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017	56	2017
Spintastic: Spin-based stochastic logic for energy-efficient computing R Venkatesan, S Venkataramani, X Fong, K Roy, A Raghunathan 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015	49	2015

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