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Sumedh Sathaye
Sumedh Sathaye
Distinguished Engineer, Dell Technologies
Dirección de correo verificada de dell.com
Título
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Citado por
Año
Dynamic binary translation and optimization
K Ebcioglu, E Altman, M Gschwind, S Sathaye
IEEE Transactions on computers 50 (6), 529-548, 2001
2292001
Dynamic and transparent binary translation
M Gschwind, ER Altman, S Sathaye, P Ledak, D Appenzeller
Computer 33 (3), 54-59, 2000
1932000
Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system
E Altman, K Ebcioglu, M Gschwind, S Sathaye
US Patent 6,349,361, 2002
1902002
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ...
US Patent 6,779,049, 2004
1092004
Advances and future challenges in binary translation and optimization
ER Altman, K Ebcioglu, M Gschwind, S Sathaye
Proceedings of the IEEE 89 (11), 1710-1722, 2001
1072001
Instruction fetch mechanisms for VLIW architectures with compressed encodings
TM Conte, S Banerjia, SY Larin, KN Menezes, SW Sathaye
Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996
1061996
Method and apparatus for implementing execution predicates in a computer processing system
MK Gschwind, S Sathaye
US Patent 6,513,109, 2003
972003
BOA: The architecture of a binary translation processor
E Altman, M Gschwind, S Sathaye, S Kosonocky, A Bright, J Fritts, ...
IBM Research Report RC 21665, 2000
802000
Method and system for multiprocessor emulation on a multiprocessor host system
ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ...
US Patent 7,496,494, 2009
772009
Dynamic rescheduling: A technique for object code compatibility in VLIW architectures
TM Conte, SW Sathaye
Proceedings of the 28th Annual International Symposium on Microarchitecture …, 1995
731995
Optimizations and oracle parallelism with dynamic translation
K Ebcioglu, ER Altman, S Sathaye, M Gschwind
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999
641999
BOA: Targeting multi-gigahertz with binary translation
S Sathaye, P Ledak, J Leblanc, S Kosonocky, M Gschwind, J Fritts, Z Filan, ...
Proc. of the 1999 Workshop on Binary Translation, 2-11, 1999
631999
Structure for instruction cache trace formation
GT Davis, RW Doing, JD Jabusch, MVVA Krishna, B Olsson, EF Robinson, ...
US Patent App. 12/131,442, 2008
582008
Binary translation and architecture convergence issues for IBM System/390
M Gschwind, K Ebcioğlu, E Altman, S Sathaye
Proceedings of the 14th international conference on Supercomputing, 336-347, 2000
552000
Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors
ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ...
US Patent 6,907,477, 2005
532005
Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
E Altman, M Gschwind, D Prener, J Rivers, S Sathaye, JD Wellman, ...
US Patent App. 11/047,983, 2006
472006
Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host
ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ...
US Patent 7,953,588, 2011
462011
Execution-based scheduling for VLIW architectures
K Ebcioğlu, ER Altman, S Sathaye, M Gschwind
Euro-Par’99 Parallel Processing: 5th International Euro-Par Conference …, 1999
451999
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design
TM Conte, KN Menezes, SW Sathaye, MC Toburen
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (2), 129-137, 2000
442000
System and method of execution of register pointer instructions ahead of instruction issues
E Altman, MK Gschwind, JA Rivers, SW Sathaye, JD Wellman, V Zyuban
US Patent 7,496,733, 2009
372009
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