FP-BNN: Binarized neural network on FPGA S Liang, S Yin, L Liu, W Luk, S Wei Neurocomputing 275, 1072-1086, 2018 | 340 | 2018 |
Deep convolutional neural network architecture with reconfigurable computation patterns F Tu, S Yin, P Ouyang, S Tang, L Liu, S Wei IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 330 | 2017 |
A review, classification, and comparative evaluation of approximate arithmetic circuits H Jiang, C Liu, L Liu, F Lombardi, J Han ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (4), 1-34, 2017 | 271 | 2017 |
Approximate arithmetic circuits: A survey, characterization, and recent applications H Jiang, FJH Santiago, H Mo, L Liu, J Han Proceedings of the IEEE 108 (12), 2108-2135, 2020 | 248 | 2020 |
A high energy efficient reconfigurable hybrid neural network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, S Zheng, T Lu, J Gu, L Liu, S Wei IEEE Journal of Solid-State Circuits 53 (4), 968-982, 2017 | 219 | 2017 |
A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin, S Wei ACM Computing Surveys (CSUR) 52 (6), 1-39, 2019 | 209 | 2019 |
Analog circuit optimization system based on hybrid evolutionary algorithms B Liu, Y Wang, Z Yu, L Liu, M Li, Z Wang, J Lu, FV Fernández Integration 42 (2), 137-148, 2009 | 209 | 2009 |
A crop monitoring system based on wireless sensor network L Zhao, S Yin, L Liu, Z Zhang, S Wei Procedia Environmental Sciences 11, 558-565, 2011 | 192* | 2011 |
Highly efficient architecture of NewHope-NIST on FPGA using low-complexity NTT/INTT N Zhang, B Yang, C Chen, S Yin, S Wei, L Liu IACR Transactions on Cryptographic Hardware and Embedded Systems, 49-72, 2020 | 148 | 2020 |
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, L Liu, S Wei 2017 Symposium on VLSI Circuits, C26-C27, 2017 | 103 | 2017 |
A 5.1 pJ/neuron 127.3 us/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65nm CMOS R Guo, Y Liu, S Zheng, SY Wu, P Ouyang, WS Khwa, X Chen, JJ Chen, ... 2019 Symposium on VLSI Circuits, C120-C121, 2019 | 102 | 2019 |
RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM F Tu, W Wu, S Yin, L Liu, S Wei 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 86 | 2018 |
Polyhedral model based mapping optimization of loop nests for CGRAs D Liu, S Yin, L Liu, S Wei Proceedings of the 50th Annual Design Automation Conference, 1-8, 2013 | 82 | 2013 |
A 28nm 29.2 TFLOPS/W BF16 and 36.5 TOPS/W INT8 reconfigurable digital CIM processor with unified FP/INT pipeline and bitwise in-memory booth multiplication for cloud deep … F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 77 | 2022 |
A 141 uw, 2.46 pj/neuron binarized convolutional neural network based self-learning speech recognition processor in 28nm cmos S Yin, P Ouyang, S Zheng, D Song, X Li, L Liu, S Wei 2018 IEEE Symposium on VLSI Circuits, 139-140, 2018 | 77 | 2018 |
LWRpro: An energy-efficient configurable crypto-processor for module-LWR Y Zhu, M Zhu, B Yang, W Zhu, C Deng, C Chen, S Wei, L Liu IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3), 1146-1159, 2021 | 76* | 2021 |
An implementation of fast-locking and wide-range 11-bit reversible SAR DLL L Wang, L Liu, H Chen IEEE Transactions on Circuits and Systems II: Express Briefs 57 (6), 421-425, 2010 | 66 | 2010 |
A high-performance and energy-efficient FIR adaptive filter using approximate distributed arithmetic circuits H Jiang, L Liu, PP Jonker, DG Elliott, F Lombardi, J Han IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 313-326, 2018 | 65 | 2018 |
Fast traffic sign recognition with a rotation invariant binary pattern based feature S Yin, P Ouyang, L Liu, Y Guo, S Wei Sensors 15 (1), 2161-2180, 2015 | 64 | 2015 |
An energy-efficient reconfigurable processor for binary-and ternary-weight neural networks with flexible data bit width S Yin, P Ouyang, J Yang, T Lu, X Li, L Liu, S Wei IEEE Journal of Solid-State Circuits 54 (4), 1120-1136, 2018 | 60 | 2018 |