Björn Franke
Björn Franke
Professor in the School of Informatics, University of Edinburgh
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Using machine learning to focus iterative optimization
F Agakov, E Bonilla, J Cavazos, B Franke, G Fursin, MFP O'Boyle, ...
International Symposium on Code Generation and Optimization (CGO'06), 11 pp.-305, 2006
Towards a holistic approach to auto-parallelization: integrating profile-driven parallelism detection and machine-learning based mapping
G Tournavitis, Z Wang, B Franke, MFP O'Boyle
ACM Sigplan notices 44 (6), 177-187, 2009
Fast compiler optimisation evaluation using code-feature based performance prediction
C Dubach, J Cavazos, B Franke, G Fursin, MFP O'Boyle, O Temam
Proceedings of the 4th international conference on Computing frontiers, 131-142, 2007
Integrating profile-driven parallelism detection and machine-learning-based mapping
Z Wang, G Tournavitis, B Franke, MFP O'boyle
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-26, 2014
Probabilistic source-level optimisation of embedded programs
B Franke, M O'Boyle, J Thomson, G Fursin
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages …, 2005
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
KT Sundararajan, V Porpodas, TM Jones, NP Topham, B Franke
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information
G Tournavitis, B Franke
Proceedings of the 19th international conference on Parallel architectures …, 2010
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator
I Böhm, TJK Edler von Koch, SC Kyle, B Franke, N Topham
ACM SIGPLAN Notices 46 (6), 74-85, 2011
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
I Böhm, B Franke, N Topham
2010 International Conference on Embedded Computer Systems: Architectures …, 2010
Integrating algorithmic parameters into benchmarking and design space exploration in 3D scene understanding
B Bodin, L Nardi, MZ Zia, H Wagstaff, G Sreekar Shenoy, M Emani, ...
Proceedings of the 2016 International Conference on Parallel Architectures …, 2016
Array recovery and high-level transformations for DSP applications
B Franke, M O'boyle
ACM Transactions on Embedded Computing Systems (TECS) 2 (2), 132-162, 2003
Fast cycle-approximate instruction set simulation
B Franke
Proceedings of the 11th international workshop on Software & compilers for …, 2008
Navigating the landscape for real-time localization and mapping for robotics and virtual and augmented reality
S Saeedi, B Bodin, H Wagstaff, A Nisbet, L Nardi, J Mawer, N Melot, ...
Proceedings of the IEEE 106 (11), 2020-2039, 2018
Performance aware convolutional neural network channel pruning for embedded GPUs
V Radu, K Kaszyk, Y Wen, J Turner, J Cano, EJ Crowley, B Franke, ...
2019 IEEE International Symposium on Workload Characterization (IISWC), 24-34, 2019
Exploiting function similarity for code size reduction
TJK Edler von Koch, B Franke, P Bhandarkar, A Dasgupta
Proceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers …, 2014
Compiler transformation of pointers to explicit array accesses in DSP applications
B Franke, M O’Boyle
International Conference on Compiler Construction, 69-85, 2001
An end-to-end design flow for automated instruction set extension and complex instruction selection based on GCC
O Almer, R Bennett, I Böhm, A Murray, X Qu, M Zuluaga, B Franke, ...
Proceedings of the First International Workshop on GCC Research …, 2009
Reducing training time in a one-shot machine learning-based compiler
J Thomson, M O’Boyle, G Fursin, B Franke
International workshop on languages and compilers for parallel computing …, 2009
Scalable multi-core simulation using parallel dynamic binary translation
O Almer, I Böhm, TE Von Koch, B Franke, S Kyle, V Seeker, C Thompson, ...
2011 International Conference on Embedded Computer Systems: Architectures …, 2011
Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description
H Wagstaff, M Gould, B Franke, N Topham
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
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