| Software defined monitoring of application protocols L Kekely, J Kučera, V Puš, J Kořenek, AV Vasilakos IEEE Transactions on Computers 65 (2), 615-626, 2015 | 72 | 2015 |
| Fast and scalable packet classification using perfect hash functions V Puš, J Korenek Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009 | 55 | 2009 |
| Configurable FPGA packet parser for terabit networks with guaranteed wire-speed throughput J Cabal, P Benáček, L Kekely, M Kekely, V Puš, J Kořenek Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 35 | 2018 |
| P4-To-VHDL: Automatic generation of high-speed input and output network blocks P Benáček, V Puš, H Kubátová, T Čejka Microprocessors and Microsystems 56, 22-33, 2018 | 35 | 2018 |
| Low-latency modular packet header parser for FPGA V Pus, L Kekely, J Korenek Proceedings of the eighth ACM/IEEE symposium on Architectures for networking …, 2012 | 31 | 2012 |
| Netbench: Framework for evaluation of packet processing algorithms V Pus, J Tobola, V Kosar, J Kastil, J Korenek 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and …, 2011 | 28 | 2011 |
| Design methodology of configurable high performance packet parser for FPGA V Puš, L Kekely, J Kořenek 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 23 | 2014 |
| High-speed regular expression matching with pipelined automata D Matoušek, J Kořenek, V Puš 2016 International Conference on Field-Programmable Technology (FPT), 93-100, 2016 | 16 | 2016 |
| Hardware accelerated flow measurement of 100 Gb ethernet V Puš, P Velan, L Kekely, J Kořenek, P Minařík 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015 | 12 | 2015 |
| Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring L Kekely, V Puš, P Benáček, J Kořenek 2014 24th International Conference on Field Programmable Logic and …, 2014 | 11 | 2014 |
| Line rate programmable packet processing in 100gb networks P Benáček, V Puš, J Kořenek, M Kekely 2017 27th International Conference on Field Programmable Logic and …, 2017 | 10 | 2017 |
| Multi buses: Theory and practical considerations of data bus width scaling in FPGAs L Kekely, J Cabal, V Puš, J Kořenek 2020 23rd Euromicro Conference on Digital System Design (DSD), 49-56, 2020 | 9 | 2020 |
| Memory optimization for packet classification algorithms J Blaho, J Kořenek, V Puš Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking …, 2009 | 7 | 2009 |
| CRC based hashing in FPGA using DSP blocks T Závodník, L Kekely, V Puš 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 6 | 2014 |
| High-density network flow monitoring P Velan, V Puš 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015 | 5 | 2015 |
| Hardware acceleration for measurements in 100 gb/s networks V Puš Dependable Networks and Services: 6th IFIP WG 6.6 International Conference …, 2012 | 5 | 2012 |
| Hardware architecture for packet classification with prefix coloring V Puš, M Kajan, J KoŸenek 14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011 | 4 | 2011 |
| Verification of generated rtl from p4 source code R Iša, P Benáček, V Puš 2018 IEEE 26th International Conference on Network Protocols (ICNP), 444-445, 2018 | 3 | 2018 |
| Packet Classification Algorithms. V Puš Information Sciences & Technologies: Bulletin of the ACM Slovakia 4 (4), 2012 | 3 | 2012 |
| Memory optimizations for packet classification algorithms in FPGA V Puš, J Blaho, J Kořenek 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010 | 2 | 2010 |
