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Saša Tomić
Saša Tomić
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EazyHTM: Eager-lazy hardware transactional memory
S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ...
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
1572009
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 9,857,986, 2018
802018
Cooperative data deduplication in a solid state storage array
TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic
US Patent 10,013,169, 2018
732018
Metadata hardening and parity accumulation for log-structured arrays
I Koltsidas, CJ Camp, N Ioannou, RA Pletka, AK Kourtis, S Tomic, ...
US Patent 10,437,670, 2019
532019
Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads
N Ioannou, N Papandreou, RA Pletka, S Tomic
US Patent 10,170,195, 2019
44*2019
Reducing unnecessary calibration of a memory unit for which the error count margin has been exceeded
N Ioannou, N Papandreou, RA Pletka, S Tomic
US Patent 10,824,352, 2020
422020
Characterization and analysis of bit errors in 3D TLC NAND flash memory
N Papandreou, H Pozidis, T Parnell, N Ioannou, R Pletka, S Tomic, ...
2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019
392019
Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
CJ Camp, TJ Fisher, AD Fry, N Ioannou, R Pletka, S Tomic
US Patent 9,563,373, 2017
392017
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
352016
Vertical sub-micron CMOS transistors on (110),(111),(311),(511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same
L Forbes, W Noble, A Reinberg
US Patent App. 10/222,997, 2004
352004
Multi-lug socket tool
L Boston
US Patent 6,668,685, 2003
34*2003
Regrouping data during relocation to facilitate write amplification reduction
RS Ahmed, CJ Camp, TJ Fisher, AD Fry, N Ioannou, J Ma, MR Orr, ...
US Patent 10,884,914, 2021
312021
Increasing storage efficiency of a data protection technique
RA Pletka, RI Stoica, I Koltsidas, N Ioannou, S Tomic, AK Kourtis, ...
US Patent 10,592,173, 2020
312020
Non-volatile memory controller cache architecture with support for separation of data streams
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic, ...
US Patent 9,779,021, 2017
302017
Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 9,632,927, 2017
282017
The velox transactional memory stack
P Felber, E Riviere, WM Moreira, D Harmanci, P Marlier, S Diestelhorst, ...
Micro, IEEE 30 (5), 76-87, 2010
28*2010
Non-volatile memory system having an increased effective number of supported heat levels
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 10,078,582, 2018
24*2018
Techniques for dynamically adjusting over-provisioning space of a flash controller based on workload characteristics
CJ Camp, TJ Fisher, AD Fry, N Ioannou, T Parnell, RA Pletka, S Tomic
US Patent 10,592,110, 2020
232020
Management of next-generation NAND flash to achieve enterprise-level endurance and latency targets
R Pletka, I Koltsidas, N Ioannou, S Tomić, N Papandreou, T Parnell, ...
ACM Transactions on Storage (TOS) 14 (4), 1-25, 2018
232018
Adaptive read voltage threshold calibration in non-volatile memory
RA Pletka, N Papandreou, S Tomic, N Ioannou, C Pozidis, T Fisher, ...
US Patent 10,699,791, 2020
222020
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