A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing Q Zhu, B Akin, HE Sumbul, F Sadi, JC Hoe, L Pileggi, F Franchetti 2013 IEEE international 3D systems integration conference (3DIC), 1-7, 2013 | 150 | 2013 |
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware Q Zhu, T Graf, HE Sumbul, L Pileggi, F Franchetti 2013 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2013 | 137 | 2013 |
Efficient and secure intellectual property (IP) design with split fabrication K Vaidyanathan, R Liu, E Sumbul, Q Zhu, F Franchetti, L Pileggi 2014 IEEE international symposium on hardware-oriented security and trust …, 2014 | 86 | 2014 |
3DIC memory chips including computational logic-in-memory for performing accelerated data processing F Franchetti, Q Zhu, LT Pileggi US Patent 9,286,216, 2016 | 85 | 2016 |
Virtual linebuffers for image signal processors Q Zhu, O Shacham, JR Redgrave, DF Finchelstein, A Meixner US Patent 9,749,548, 2017 | 53 | 2017 |
Architecture for high performance, power efficient, programmable image processing Q Zhu, O Shacham, A Meixner, JR Redgrave, DF Finchelstein, ... US Patent 9,965,824, 2018 | 43 | 2018 |
Line buffer unit for image processor N Desai, A Meixner, Q Zhu, JR Redgrave, O Shacham, DF Finchelstein US Patent 9,756,268, 2017 | 34 | 2017 |
Design automation framework for application-specific logic-in-memory blocks Q Zhu, K Vaidyanathan, O Shacham, M Horowitz, L Pileggi, F Franchetti 2012 IEEE 23rd International Conference on Application-Specific Systems …, 2012 | 34 | 2012 |
Two dimensional shift array for image processor O Shacham, JR Redgrave, A Meixner, Q Zhu, DF Finchelstein, ... US Patent 9,769,356, 2017 | 29 | 2017 |
Energy efficient processor core architecture for image processor A Meixner, JR Redgrave, O Shacham, DF Finchelstein, Q Zhu US Patent 9,772,852, 2017 | 27 | 2017 |
Sheet generator for image processor A Meixner, JR Redgrave, O Shacham, Q Zhu, DF Finchelstein US Patent 10,291,813, 2019 | 26 | 2019 |
Virtual image processor instruction set architecture (isa) and memory model and exemplary target hardware having a two-dimensional shift array structure A Meixner, O Shacham, D Patterson, DF Finchelstein, Q Zhu, ... US Patent 10,095,479, 2018 | 26 | 2018 |
Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip K Vaidyanathan, Q Zhu, L Liebmann, K Lai, S Wu, R Liu, Y Liu, A Strojwas, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (1), 011007-011007, 2015 | 16 | 2015 |
Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory Q Zhu, CR Berger, EL Turner, L Pileggi, F Franchetti 2012 IEEE International Conference on Acoustics, Speech and Signal …, 2012 | 11 | 2012 |
Application-specific logic-in-memory for polar format synthetic aperture radar Q Zhu, EL Turnerz, CR Bergery, L Pileggi, F Franchetti Proc. High Performance Embedded Computing (HPEC), 2011 | 9 | 2011 |
Compiler managed memory for image processor A Meixner, P Hyunchul, Q Zhu, JR Redgrave US Patent 10,204,396, 2019 | 8 | 2019 |
A robust radio frequency identification system enhanced with spread spectrum technique Z Qiuling, Z Chun, L Zhongqi, W Jingchao, L Fule, W Zhihua 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 37-40, 2009 | 8 | 2009 |
Fazle Sadi, James C. Hoe, Larry Pileggi, and Franz Franchetti. 2013. A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing Q Zhu, B Akin, HE Sumbul IEEE International 3D Systems Integration Conference (3DIC’13), 1-7, 0 | 7 | |
Determination of per line buffer unit memory allocation P Hyunchul, A Meixner, Q Zhu, W Mark US Patent 10,430,919, 2019 | 6 | 2019 |
A synthesis methodology for application-specific logic-in-memory designs HE Sumbul, K Vaidyanathan, Q Zhu, F Franchetti, L Pileggi Proceedings of the 52Nd Annual Design Automation Conference, 1-6, 2015 | 6 | 2015 |