Milos Stanisavljevic
Milos Stanisavljevic
Co-founder and Principal Digital Architect, Axelera AI
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Multilevel-cell phase-change memory: A viable technology
A Athmanathan, M Stanisavljevic, N Papandreou, H Pozidis, E Eleftheriou
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (1 …, 2016
HERMES Core–A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
A high-performance system for robust stain normalization of whole-slide images in histopathology
A Anghel, M Stanisavljevic, S Andani, N Papandreou, JH Rüschoff, P Wild, ...
Frontiers in medicine 6, 193, 2019
Reliability of nanoscale circuits and systems: methodologies and circuit architectures
M Stanisavljević, A Schmid, Y Leblebici
Springer Science & Business Media, 2010
HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, M Brändli, ...
IEEE Journal of Solid-State Circuits 57 (4), 1027-1038, 2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
M Le Gallo, R Khaddam-Aljameh, M Stanisavljevic, A Vasilopoulos, ...
Nature Electronics 6 (9), 680-693, 2023
Demonstration of reliable triple-level-cell (TLC) phase-change memory
M Stanisavljevic, H Pozidis, A Athmanathan, N Papandreou, ...
2016 IEEE 8th international memory workshop (IMW), 1-4, 2016
Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures
M Stanisavljevic, A Athmanathan, N Papandreou, H Pozidis, E Eleftheriou
2015 IEEE International Reliability Physics Symposium, 5B. 6.1-5B. 6.6, 2015
Deep learning acceleration based on in-memory computing
E Eleftheriou, M Le Gallo, SR Nandakumar, C Piveteau, I Boybat, V Joshi, ...
IBM Journal of Research and Development 63 (6), 7: 1-7: 16, 2019
Optimization of the averaging reliability technique using low redundancy factors for nanoscale technologies
M Stanisavljevic, A Schmid, Y Leblebici
IEEE Transactions on Nanotechnology 8 (3), 379-390, 2008
Fault-tolerance of robust feed-forward architecture using single-ended and differential deep-submicron circuits under massive defect density
M Stanisavljevic, A Schmid, Y Leblebici
The 2006 IEEE International Joint Conference on Neural Network Proceedings …, 2006
Toward software-equivalent accuracy on transformer-based deep neural networks with analog memory devices
K Spoon, H Tsai, A Chen, MJ Rasch, S Ambrogio, C Mackin, A Fasoli, ...
Frontiers in Computational Neuroscience 15, 675741, 2021
Optimization of nanoelectronic systems’ reliability under massive defect density using cascaded R-fold modular redundancy
M Stanisavljevic, A Schmid, Y Leblebici
Nanotechnology 19 (46), 465202, 2008
A heterogeneous and programmable compute-in-memory accelerator architecture for analog-AI using dense 2-D mesh
S Jain, H Tsai, CT Chen, R Muralidhar, I Boybat, MM Frank, S Woźniak, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (1), 114-127, 2022
Phase change memory reliability: A signal processing and coding perspective
H Pozidis, T Mittelholzer, N Papandreou, T Parnell, M Stanisavljevic
IEEE Transactions on Magnetics 51 (4), 1-7, 2015
The complete time/temperature dependence of IV drift in PCM devices
M Le Gallo, A Sebastian, D Krebs, M Stanisavljevic, E Eleftheriou
2016 IEEE International Reliability Physics Symposium (IRPS), MY-1-1-MY-1-6, 2016
A 6-bit drift-resilient readout scheme for multi-level phase-change memory
A Athmanathan, M Stanisavljevic, J Cheon, S Kang, C Ahn, J Yoon, ...
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 137-140, 2014
Open block characterization and read voltage calibration of 3D QLC NAND flash
N Papandreou, H Pozidis, N Ioannou, T Parnell, R Pletka, ...
2020 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2020
Optimization of nanoelectronic systems reliability under massive defect density using distributed R-fold modular redundancy (DRMR)
M Stanisavljevic, A Schmid, Y Leblebici
2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009
Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect
N Papandreou, N Ioannou, T Parnell, R Pletka, M Stanisavljevic, R Stoica, ...
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2019
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