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Natalie Enright Jerger
Natalie Enright Jerger
Dirección de correo verificada de eecg.toronto.edu - Página principal
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Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
R Marculescu, UY Ogras, LS Peh, N Enright Jerger, Y Hoskote
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2009
9062009
Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing
J Albericio, P Judd, T Hetherington, T Aamodt, N Enright Jerger, ...
International Symposium on Computer Architecture, 2016
8972016
On-chip networks
N Enright Jerger, LS Peh
Synthesis Lectures on Computer Architecture 4 (1), 1-141, 2009
325*2009
Virtual circuit tree multicasting: A case for on-chip hardware multicast support
N Enright Jerger, LS Peh, M Lipasti
Computer Architecture, 2008. ISCA'08. 35th International Symposium on, 229-240, 2008
316*2008
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
S Ma, N Enright Jerger, Z Wang
Computer Architecture (ISCA), 2011 38th Annual International Symposium on …, 2011
2242011
Load Value Approximation
J San Miguel, M Badr, N Enright Jerger
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium …, 2014
2212014
Scarab: A single cycle adaptive routing and bufferless network
M Hayenga, N Enright Jerger, M Lipasti
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
2112009
On-Chip Networks
N Enright Jerger, T Krishna, LS Peh
Synthesis Lectures on Computer Architecture 12 (3), 1-210, 2017
208*2017
Achieving predictable performance through better memory controller placement in many-core CMPs
D Abts, ND Enright Jerger, J Kim, D Gibson, MH Lipasti
ACM SIGARCH Computer Architecture News 37 (3), 451-461, 2009
2082009
Circuit-Switched Coherence
N Enright Jerger, M Lipasti, LS Peh
IEEE Computer Architecture Letters, v. 6 n. 1, 2007
190*2007
Circuit-switched coherence
ND Enright Jerger, LS Peh, MH Lipasti
Proceedings of the Second ACM/IEEE International Symposium on Networks-on …, 2008
189*2008
Enabling interposer-based disintegration of multi-core processors
A Kannan, N Enright Jerger, GH Loh
Proceedings of the 48th International Symposium on Microarchitecture, 546-558, 2015
1882015
Doppelgänger: a cache for approximate computing
J San Miguel, J Albericio, A Moshovos, N Enright Jerger
Proceedings of the 48th International Symposium on Microarchitecture, 50-61, 2015
1672015
SynFull: synthetic traffic models capturing cache coherent behaviour
M Badr, N Enright Jerger
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on …, 2014
1462014
Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets
P Judd, J Albericio, T Hetherington, T Aamodt, N Enright Jerger, ...
arXiv preprint arXiv:1511.05236, 2015
1322015
MEMORY IN DEEP NEURAL NETS
P Judd, J Albericio, T Hetherington, T Aamodt, N Enright Jerger, ...
arXiv preprint arXiv:1511.05236, 2015
1322015
Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks
P Judd, J Albericio, T Hetherington, T Aamodt, N Enright Jerger, ...
Workshop on Approximate Computing, 2016
1262016
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
N Enright Jerger, A Kannan, Z Li, GH Loh
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium …, 2014
122*2014
Modular Routing Design for Chiplet-based Systems
J Yin, Z Lin, O Kayiran, M Poremba, MSB Altaf, N Enright Jerger, GH Loh
International Symposium on Computer Architecture, 2018
1212018
Whole Packet Forwarding: Efficient Design of Fully Adaptive Routing Algorithms for Networks-on-Chip
S Ma, N Enright Jerger, Z Wang
International Symposium on High Performance Computer Architecture, 2012
1112012
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