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Matthias Sauer
Matthias Sauer
Advantest Europe GmbH
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Año
A flexible framework for the automatic generation of SBST programs
A Riefert, R Cantoro, M Sauer, MS Reorda, B Becker
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016
662016
Small-delay-fault ATPG with waveform accuracy
M Sauer, A Czutro, I Polian, B Becker
Proceedings of the International Conference on Computer-Aided Design, 30-36, 2012
622012
Equivalence checking of partial designs using dependency quantified Boolean formulae
K Gitina, S Reimer, M Sauer, R Wimmer, C Scholl, B Becker
2013 IEEE 31st International Conference on Computer Design (ICCD), 396-403, 2013
542013
Solving DQBF through quantifier elimination
K Gitina, R Wimmer, S Reimer, M Sauer, C Scholl, B Becker
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
452015
Exploring the mysteries of system-level test
I Polian, J Anders, S Becker, P Bernardi, K Chakrabarty, N ElHamawy, ...
2020 IEEE 29th Asian Test Symposium (ATS), 1-6, 2020
362020
Efficient SAT-based search for longest sensitisable paths
M Sauer, J Jiang, A Czutro, I Polian, B Becker
2011 Asian Test Symposium, 108-113, 2011
342011
PHAETON: A SAT-based framework for timing-aware path sensitization
M Sauer, B Becker, I Polian
IEEE Transactions on Computers 65 (6), 1869-1881, 2015
312015
On the automatic generation of SBST test programs for in-field test
A Riefert, R Cantoro, M Sauer, MS Reorda, B Becker
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
312015
An effective approach to automatic functional processor test generation for small-delay faults
A Riefert, L Ciganda, M Sauer, P Bernardi, MS Reorda, B Becker
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
302014
Towards the formal verification of security properties of a network-on-chip router
J Sepulveda, D Aboul-Hassan, G Sigl, B Becker, M Sauer
2018 IEEE 23rd European Test Symposium (ETS), 1-6, 2018
292018
Specification and verification of security in reconfigurable scan networks
MA Kochte, M Sauer, LR Gomez, P Raiola, B Becker, HJ Wunderlich
2017 22nd IEEE European Test Symposium (ETS), 1-6, 2017
282017
Functional test of small-delay faults using SAT and Craig interpolation
M Sauer, S Kupferschmid, A Czutro, I Polian, S Reddy, B Becker
2012 IEEE International Test Conference, 1-8, 2012
272012
On the optimality of K longest path generation algorithm under memory constraints
J Jiang, M Sauer, A Czutro, B Becker, I Polian
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 418-423, 2012
272012
SAT-based analysis of sensitisable paths
M Sauer, A Czutro, T Schubert, S Hillebrecht, I Polian, B Becker
14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011
252011
Multi-cycle circuit parameter independent ATPG for interconnect open defects
D Erb, K Scheibler, M Sauer, SM Reddy, B Becker
2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015
242015
Formal verification of secure reconfigurable scan network infrastructure
MA Kochte, R Baranowski, M Sauer, B Becker, HJ Wunderlich
2016 21th IEEE European Test Symposium (ETS), 1-6, 2016
232016
Sensitized path PUF: A lightweight embedded physical unclonable function
M Sauer, P Raiola, L Feiten, B Becker, U Rührmair, I Polian
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
222017
Systemic frequency biases in ring oscillator pufs on fpgas
L Feiten, J Oesterle, T Martin, M Sauer, B Becker
IEEE Transactions on Multi-Scale Computing Systems 2 (3), 174-185, 2016
222016
Early-life-failure detection using SAT-based ATPG
M Sauer, YM Kim, J Seomun, HO Kim, KT Do, JY Choi, KS Kim, S Mitra, ...
2013 IEEE International Test Conference (ITC), 1-10, 2013
212013
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
M Sauer, S Reimer, T Schubert, I Polian, B Becker
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 448-453, 2013
202013
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