| P4: Phase-based power/performance prediction of heterogeneous systems via neural networks Y Kim, P Mercati, A More, E Shriver, T Rosing 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 683-690, 2017 | 35 | 2017 |
| Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual … S Khare, D Somasekhar, A More, DS Dunning, NY Borkar, SY Borkar US Patent 9,992,135, 2018 | 32 | 2018 |
| Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation S Nilakantan, K Sangaiah, A More, G Salvadory, B Taskin, M Hempstead 2015 IEEE International Symposium on Performance Analysis of Systems and …, 2015 | 28 | 2015 |
| Application performance prediction and optimization under cache allocation technology Y Kim, A More, E Shriver, T Rosing 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 26 | 2019 |
| PIUMA: programmable integrated unified memory architecture S Aananthakrishnan, NK Ahmed, V Cave, M Cintra, Y Demir, KD Bois, ... arXiv preprint arXiv:2010.06277, 2020 | 25 | 2020 |
| Synchrotrace: Synchronization-aware architecture-agnostic traces for lightweight multicore simulation of cmp and hpc workloads K Sangaiah, M Lui, R Jagtap, S Diestelhorst, S Nilakantan, A More, ... ACM Transactions on Architecture and Code Optimization (TACO) 15 (1), 1-26, 2018 | 18 | 2018 |
| Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC A More, B Taskin 23rd IEEE International SOC Conference, 447-452, 2010 | 16 | 2010 |
| Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data KW Kwon, V Kozhikkottu, SP Park, A More, WP Griffin, R Pawlowski, ... US Patent App. 15/477,072, 2018 | 13 | 2018 |
| Instruction set architecture to facilitate energy-efficient computing for exascale architectures JB Fryman, JM Howard, P Suresh, BM Nagasundaram, ... US Patent App. 15/940,768, 2019 | 12 | 2019 |
| Wireless interconnects for inter-tier communication on 3D ICs A More, B Taskin The 40th European Microwave Conference, 105-108, 2010 | 12 | 2010 |
| 3-D parasitic modeling for rotary interconnects V Honkote, A More, B Taskin 2012 25th International Conference on VLSI Design, 137-142, 2012 | 9 | 2012 |
| Vertical arbitration-free 3-D NoCs A More, V Pano, B Taskin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 8 | 2017 |
| Traleika glacier: A hardware-software co-designed approach to exascale computing V Cavé, R Clédat, P Griffin, A More, B Seshasayee, S Borkar, S Chatterjee, ... Parallel Computing 64, 33-49, 2017 | 8 | 2017 |
| Simulation based study of wireless RF interconnects for practical cmos implementation A More, B Taskin Proceedings of the 12th ACM/IEEE international workshop on System level …, 2010 | 8 | 2010 |
| Leakage current analysis for intra-chip wireless interconnects A More, B Taskin 2010 11th International Symposium on Quality Electronic Design (ISQED), 49-53, 2010 | 8 | 2010 |
| EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs A More, B Taskin 2011 IEEE 29th International Conference on Computer Design (ICCD), 19-24, 2011 | 7 | 2011 |
| Simulation based feasibility study of wireless RF interconnects for 3D ICs A More, B Taskin 2010 IEEE Computer Society Annual Symposium on VLSI, 228-231, 2010 | 7 | 2010 |
| A unified design methodology for a hybrid wireless 2-D NoC A More, B Taskin 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 640-643, 2012 | 6 | 2012 |
| Architecture for on-die interconnect S Khare, A More, D Somasekhar, DS Dunning US Patent 9,287,208, 2016 | 5 | 2016 |
| Network-on-Chip (NoC) Architectures for Exa-scale Chip-Multi-Processors (CMPs) A More Drexel University, 2013 | 5 | 2013 |
Baris TaskinProfessor of ECE, Drexel UniversityDirección de correo verificada de coe.drexel.edu
