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Aleš Smrčka
Aleš Smrčka
Assistant professor of Computer Science, Brno University of Technology
Dirección de correo verificada de fit.vutbr.cz
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Verifying parametrised hardware designs via counter automata
A Smrčka, T Vojnar
Haifa Verification Conference, 51-68, 2007
222007
Verifying concurrent programs using contracts
RJ Dias, C Ferreira, J Fiedor, JM Lourenço, A Smrcka, DG Sousa, ...
2017 IEEE International Conference on Software Testing, Verification and …, 2017
182017
Advances in the ANaConDA framework for dynamic analysis and testing of concurrent C/C++ programs
J Fiedor, M Mužikovská, A Smrčka, O Vašíček, T Vojnar
Proceedings of the 27th ACM SIGSOFT International Symposium on Software …, 2018
102018
Automatic formal correspondence checking of ISA and RTL microprocessor description
L Charvát, A Smrcka, T Vojnar
2012 13th International Workshop on Microprocessor Test and Verification …, 2012
102012
The VALU3S ECSEL project: Verification and validation of automated systems safety and security
JA Agirre, L Etxeberria, R Barbosa, S Basagiannis, G Giantamidis, ...
Microprocessors and microsystems 87, 104349, 2021
92021
The VALU3S ECSEL project: verification and validation of automated systems safety and security
R Barbosa, S Basagiannis, G Giantamidis, H Becker, E Ferrari, J Jahic, ...
2020 23rd Euromicro Conference on Digital System Design (DSD), 352-359, 2020
82020
Teoretická informatika (studijní opora)
M Češka, T Vojnar, A Smrčka
Brno, FIT VUT v Brně, 2007
82007
Nástroj pro tvorbu obsahu databáze pro účely testování software
J Kotyz, A SMRČKA
Brno, CZ, 2018
72018
HADES: microprocessor hazard analysis via formal verification of parameterized systems
L Charvát, A Smrčka, T Vojnar
arXiv preprint arXiv:1612.04986, 2016
62016
Using formal verification of parameterized systems in RAW hazard analysis in microprocessors
L Charvát, A Smrcka, T Vojnar
2014 15th International Microprocessor Test and Verification Workshop, 83-89, 2014
62014
Verification of Asynchronous and Parametrized Hardware Designs
A Smrcka
Information Sciences and Technologies Bulletin of the ACM Slovakia 2 (2), 60-69, 2010
52010
Verifying VHDL designs with multiple clocks in SMV
A Smrčka, V Řehák, T Vojnar, D Šafránek, P Matoušek, Z Řehák
International Workshop on Parallel and Distributed Methods in Verification …, 2006
52006
Automatizovaná syntéza stromových struktur z reálných dat
D Želiar
Vysoké učení technické v Brně. Fakulta informačních technologií, 2019
42019
An Abstraction of Multi-port Memories with Arbitrary Addressable Units
L Charvát, A Smrčka, T Vojnar
International Conference on Computer Aided Systems Theory, 460-468, 2013
42013
Generování modelů pro testy ze zdrojových kódů
D Kraut, A SMRČKA
Diplomová práce, Vysoké učení technické v Brně, Fakulta informačních technologií, 2019
32019
Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems
L Charvát, A Smrčka, T Vojnar
International Conference on Computer Aided Systems Theory, 605-614, 2015
32015
NetLoiter: A Tool for Automated Testing of Network Applications using Fault-injection
M Rozsíval, A Smrčka
2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems …, 2023
22023
Monitorování výkonnosti systému MES PHARIS
A Ondráček, A SMRČKA
Brno, CZ, 2022
22022
Cross-domain modelling of verification and validation workflows in the large scale European research project VALU3S
T Bauer, JA Agirre, D Fürcho, W Herzner, B Hruška, M Karaca, D Pereira, ...
International Conference on Embedded Computer Systems, 368-382, 2021
22021
Rozvoj instrumentace programu při překladu
V Ševčík, A SMRČKA
Brno, CZ, 2020
22020
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