| Verifying parametrised hardware designs via counter automata A Smrčka, T Vojnar Haifa Verification Conference, 51-68, 2007 | 24 | 2007 |
| Verifying concurrent programs using contracts RJ Dias, C Ferreira, J Fiedor, JM Lourenço, A Smrcka, DG Sousa, ... 2017 IEEE International Conference on Software Testing, Verification and …, 2017 | 19 | 2017 |
| The VALU3S ECSEL project: Verification and validation of automated systems safety and security JA Agirre, L Etxeberria, R Barbosa, S Basagiannis, G Giantamidis, ... Microprocessors and microsystems 87, 104349, 2021 | 10 | 2021 |
| Advances in the ANaConDA framework for dynamic analysis and testing of concurrent C/C++ programs J Fiedor, M Mužikovská, A Smrčka, O Vašíček, T Vojnar Proceedings of the 27th ACM SIGSOFT International Symposium on Software …, 2018 | 10 | 2018 |
| Automatic formal correspondence checking of ISA and RTL microprocessor description L Charvát, A Smrcka, T Vojnar 2012 13th International Workshop on Microprocessor Test and Verification …, 2012 | 10 | 2012 |
| The VALU3S ECSEL project: verification and validation of automated systems safety and security R Barbosa, S Basagiannis, G Giantamidis, H Becker, E Ferrari, J Jahic, ... 2020 23rd Euromicro Conference on Digital System Design (DSD), 352-359, 2020 | 9 | 2020 |
| Nástroj pro tvorbu obsahu databáze pro účely testování software J Kotyz, A SMRČKA Brno, CZ, 2018 | 8 | 2018 |
| Teoretická informatika (studijní opora) M Češka, T Vojnar, A Smrčka Brno, FIT VUT v Brně, 2007 | 7 | 2007 |
| HADES: microprocessor hazard analysis via formal verification of parameterized systems L Charvát, A Smrčka, T Vojnar arXiv preprint arXiv:1612.04986, 2016 | 6 | 2016 |
| Using formal verification of parameterized systems in RAW hazard analysis in microprocessors L Charvát, A Smrcka, T Vojnar 2014 15th International Microprocessor Test and Verification Workshop, 83-89, 2014 | 6 | 2014 |
| Verification of Asynchronous and Parametrized Hardware Designs A Smrcka Information Sciences and Technologies Bulletin of the ACM Slovakia 2 (2), 60-69, 2010 | 5 | 2010 |
| Verifying VHDL designs with multiple clocks in SMV A Smrčka, V Řehák, T Vojnar, D Šafránek, P Matoušek, Z Řehák International Workshop on Parallel and Distributed Methods in Verification …, 2006 | 5 | 2006 |
| NetLoiter: a tool for automated testing of network applications using fault-injection M Rozsíval, A Smrčka 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems …, 2023 | 4 | 2023 |
| Automatizovaná syntéza stromových struktur z reálných dat D Želiar Vysoké učení technické v Brně. Fakulta informačních technologií, 2019 | 4 | 2019 |
| An Abstraction of Multi-port Memories with Arbitrary Addressable Units L Charvát, A Smrčka, T Vojnar International Conference on Computer Aided Systems Theory, 460-468, 2013 | 4 | 2013 |
| Unite: an adapter for transforming analysis tools to web services via OSLC O Vašíček, J Fiedor, T Kratochvíla, B Křena, A Smrčka, T Vojnar Proceedings of the 30th ACM Joint European Software Engineering Conference …, 2022 | 3 | 2022 |
| Rozvoj instrumentace programu při překladu V Ševčík, A SMRČKA Brno, CZ, 2020 | 3 | 2020 |
| Generování modelů pro testy ze zdrojových kódů D Kraut, A SMRČKA Diplomová práce, Vysoké učení technické v Brně, Fakulta informačních technologií, 2019 | 3 | 2019 |
| Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems L Charvát, A Smrčka, T Vojnar International Conference on Computer Aided Systems Theory, 605-614, 2015 | 3 | 2015 |
| Orchestrating Digital Twins for Distributed Manufacturing Execution Systems T Fiedor, M Hruška, A Smrčka International Conference on Computer Aided Systems Theory, 223-231, 2022 | 2 | 2022 |
