| Exploration of fault effects on formal RISC-V microarchitecture models S Tollec, M Asavoae, D Couroussé, K Heydemann, M Jan 2022 Workshop on Fault Detection and Tolerance in Cryptography (FDTC), 73-83, 2022 | 14 | 2022 |
| Fault-resistant partitioning of secure cpus for system co-verification against faults S Tollec, V Hadži, P Nasahl, M Asavoae, R Bloem, D Couroussé, ... IACR Transactions on Cryptographic Hardware and Embedded Systems 2024 (4 …, 2024 | 7 | 2024 |
| µArchiFI: Formal modeling and verification strategies for microarchitetural fault injections S Tollec, M Asavoae, D Couroussé, K Heydemann, M Jan FMCAD. 23-Formal Methods in Computer-Aided Design 2023, 2023 | 5 | 2023 |
| Formal Processor Modeling for Analyzing Safety and Security Properties B Binder, SA Bensaid, S Tollec, F Thabet, M Asavoae, M Jan Embedded Real Time Systems (ERTS), 1-10, 2022 | 3 | 2022 |
| Formal verification of processor microarchitecture to analyze system security against fault attacks S Tollec Université Paris-Saclay, 2024 | 1 | 2024 |
| Formal Analysis of Fault Injection Effects on RISC-V Microarchitecture Models S Tollec, M Asavoae, M Jan, D Couroussé, K Heydemann | | |
