Lukas Sekanina
Lukas Sekanina
Professor of Computer Science and Engineering, Brno University of Technology
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Evoapprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods
V Mrazek, R Hrbacek, Z Vasicek, L Sekanina
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Evolvable components: from theory to hardware implementations
L Sekanina
Springer Verlag, 2004
Design of power-efficient approximate multipliers for approximate artificial neural networks
V Mrazek, SS Sarwar, L Sekanina, Z Vasicek, K Roy
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2016
Efficient recognition of speed limit signs
J Torresen, JW Bakke, L Sekanina
Proceedings. The 7th International IEEE Conference on Intelligent …, 2004
Evolutionary approach to approximate digital circuits design
Z Vasicek, L Sekanina
IEEE Transactions on Evolutionary Computation 19 (3), 432-444, 2014
Virtual reconfigurable circuits for real-world applications of evolvable hardware
L Sekanina
Evolvable Systems: From Biology to Hardware: 5th International Conference …, 2003
Improving the accuracy and hardware efficiency of neural networks using approximate multipliers
MS Ansari, V Mrazek, BF Cockburn, L Sekanina, Z Vasicek, J Han
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (2), 317-328, 2019
ALWANN: Automatic layer-wise approximation of deep neural network accelerators without retraining
V Mrazek, Z Vasícek, L Sekanina, MA Hanif, M Shafique
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
Novel hardware implementation of adaptive median filters
Z Vasicek, L Sekanina
2008 11th IEEE workshop on design and diagnostics of electronic circuits and …, 2008
An evolvable hardware system in Xilinx Virtex II Pro FPGA
Z Vasicek, L Sekanina
International Journal of Innovative Computing and Applications 1 (1), 63-73, 2007
Image filter design with evolvable hardware
L Sekanina
Workshops on Applications of Evolutionary Computation, 255-266, 2002
autoax: An automatic design space exploration and circuit building methodology utilizing libraries of approximate components
V Mrazek, MA Hanif, Z Vasicek, L Sekanina, M Shafique
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
Self-reconfigurable evolvable hardware system for adaptive image processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
IEEE transactions on computers 62 (8), 1481-1493, 2013
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished
M Češka, J Matyáš, V Mrazek, L Sekanina, Z Vasicek, T Vojnar
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 416-423, 2017
Physical demonstration of polymorphic self-checking circuits
R Ruzicka, L Sekanina, R Prokop
2008 14th IEEE International On-Line Testing Symposium, 31-36, 2008
Towards evolvable systems based on the Xilinx Zynq platform
R Dobai, L Sekanina
2013 IEEE international conference on evolvable systems (ICES), 89-95, 2013
An evolvable combinational unit for FPGAs
L Sekanina, Š Friedl
Computing and informatics 23 (5-6), 461-486, 2004
Evolutionary design of gate-level polymorphic digital circuits
L Sekanina
Workshops on Applications of Evolutionary Computation, 185-194, 2005
Adaptive and energy-efficient architectures for machine learning: Challenges, opportunities, and research roadmap
M Shafique, R Hafiz, MU Javed, S Abbas, L Sekanina, Z Vasicek, ...
2017 IEEE Computer society annual symposium on VLSI (ISVLSI), 627-632, 2017
Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware
Z Vasicek, L Sekanina
Genetic Programming and Evolvable Machines 12, 305-327, 2011
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