Michael K Gschwind
Michael K Gschwind
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Synergistic processing in cell's multicore architecture
M Gschwind, HP Hofstee, B Flachs, M Hopkins, Y Watanabe, T Yamazaki
IEEE micro 26 (2), 10-24, 2006
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,081,501, 2015
The ibm blue gene/q compute chip
R Haring, M Ohmacht, T Fox, M Gschwind, D Satterfield, K Sugavanam, ...
Ieee Micro 32 (2), 48-60, 2011
Sustainable ai: Environmental implications, challenges and opportunities
CJ Wu, R Raghavendra, U Gupta, B Acun, N Ardalani, K Maeng, G Chang, ...
Proceedings of Machine Learning and Systems 4, 795-813, 2022
Optimizing compiler for the cell processor
AE Eichenbergert, K O'Brien, K O'Brien, P Wu, T Chen, PH Oden, ...
14th International Conference on Parallel Architectures and Compilation …, 2005
IBM POWER8 processor core microarchitecture
B Sinharoy, JA Van Norstrand, RJ Eickemeyer, HQ Le, J Leenstra, ...
IBM Journal of Research and Development 59 (1), 2: 1-2: 21, 2015
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
MK Gschwind, HP Hofstee, ME Hopkins
US Patent 6,839,828, 2005
Dynamic binary translation and optimization
K Ebcioglu, E Altman, M Gschwind, S Sathaye
IEEE Transactions on computers 50 (6), 529-548, 2001
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture
AE Eichenberger, JK O'Brien, KM O'Brien, P Wu, T Chen, PH Oden, ...
IBM Systems Journal 45 (1), 59-84, 2006
Chip multiprocessing and the cell broadband engine
M Gschwind
Proceedings of the 3rd conference on Computing frontiers, 1-8, 2006
Dynamic and transparent binary translation
M Gschwind, ER Altman, S Sathaye, P Ledak, D Appenzeller
Computer 33 (3), 54-59, 2000
Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system
E Altman, K Ebcioglu, M Gschwind, S Sathaye
US Patent 6,349,361, 2002
Optimizing pipelines for power and performance
V Srinivasan, D Brooks, M Gschwind, P Bose, V Zyuban, PN Strenski, ...
35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002
The Cell Broadband Engine: exploiting multiple levels of parallelism in a chip multiprocessor
M Gschwind
International journal of parallel programming 35, 233-262, 2007
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
D Brooks, P Bose, V Srinivasan, MK Gschwind, PG Emma, MG Rosenfield
IBM Journal of Research and Development 47 (5.6), 653-670, 2003
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ...
US Patent 6,779,049, 2004
Multi-addressable register file
MK Gschwind, B Olsson
US Patent 7,877,582, 2011
Advances and future challenges in binary translation and optimization
ER Altman, K Ebcioglu, M Gschwind, S Sathaye
Proceedings of the IEEE 89 (11), 1710-1722, 2001
Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture
AE Eichenberger, MK Gschwind, JA Gunnels
US Patent 8,650,240, 2014
FPGA prototyping of a RISC processor core for embedded applications
M Gschwind, V Salapura, D Maurer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2), 241-250, 2001
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